The present invention relates to a semiconductor device and a method for manufacturing the same, and can be suitably utilized for a semiconductor device including a nonvolatile memory for example.
As an electrically writable and erasable nonvolatile memory, an EEPROM (Electrically Erasable and Programmable Read Only Memory) has been widely used. These storage devices represented by a flash memory widely used at present includes, below a gate electrode of a MISFET, an electro-conductive floating gate electrode or a trapping insulating film surrounded by an oxide film, and the electric charge accumulation state in the floating gate or the trapping insulating film is made memory information which is read out as a threshold of the transistor. This trapping insulating film means an insulating film capable of accumulating the electric charge, and a silicon nitride film and the like can be cited as an example. By injection/discharging of an electric charge to/from such electric charge accumulation region, the threshold of the MISFET is shifted, and the MISFET is operated as a storage element. As this flash memory, there is a split gate type cell using a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) film. In such memory, by using a silicon nitride film as the electric charge accumulation region, compared to an electro-conductive floating gate film, there are advantages of excellence in the reliability of data retention because the electric charge is discretely accumulated, capability of making the oxide film over and below the silicon nitride film a thin film and capability of lowering the voltage of the writing/erasing operation because of excellence in the reliability of data retention, and so on.
Also, the split gate type memory cell includes a control gate electrode (selective gate electrode) formed over the semiconductor substrate through the first gate insulating film, and a memory gate electrode formed over the semiconductor substrate through the second gate insulating film including the electric charge accumulation region. Further, the split gate type memory cell includes a pair of semiconductor regions (a source region and a drain region) formed over the surface of the semiconductor substrate so as to sandwich the control gate electrode and the memory gate electrode, and the second gate insulating film has a structure called an ONO film that is a laminated structure of a silicon oxide film, a silicon nitride film, and a silicon oxide film.
Also, in Japanese Unexamined Patent Application Publication 2006-41354, a split gate type memory cell is disclosed in which an active region of a projected shape is formed over the surface of the semiconductor substrate, and a selective gate (control gate electrode) and a memory gate (memory gate electrode) are disposed so as to straddle the active region of the projected shape. Further, the selective gate 500 is formed over the active region through the gate insulating film 900, and the memory gate 550 is formed over the active region through the gate insulating film 950 that is formed of the ONO film. The ONO film has a laminated structure of a thermal oxidation silicon film, a silicon nitride film formed by the CVD method, and a silicon oxide film formed by the CVD method or the ISSG method, and has the electric charge retention function.